Learn the in-demand VLSI concepts with real-world hands-on projects.

₹11,000 to ₹4,989     56% off

Duration - 3 weeks
Placement Assistance
10+ projects
1-on-1 mentor


2 Months project work
20th July 2020


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For Whom It's for?



An integration of high end laboratory facilities, globally recognized domains and industry oriented expertise.

We have adopted a unique strategy to transform thousands of aspiring engineers with the support of industry professionals, research work, 1000+ live projects with product development exposure.

Training methodology & Delivery

Training is structured in such a way that it is focussed more on building practicle skills required for the industry. Will have online sessions on technology and mini projects as assignments.

600+ hours of skill training

This program is specially designed to build the experience by working on live projects so that student can meet employers requirement easily.

10 mini and 5 Major projects

We cover all the pre-requisites of that business model. What skills you need,what tools are needed and most importantly how much money you need to invest before getting started.

Record placements more than 95%

We have successfully nurtured careers of budding technical talent, growing high in companies like to name a few INTEL, MICROSOFT, IBM,BOSCH, SIEMENS, SAMSUNG, CISCO, Startups.

Knowledge is of no value unless you put into practice.

Internship Training At Intern Gurukul.

We have adopted a unique strategy to transform thousands of aspiring engineers with the support of industry professionals

Research work
Live projects & Product development exposure
Project Reviews
Unlimited hands-on technical skills embeds professionalism
Self-reliance and strong ethical Values
Competent Industry Ready Engineers
Personal career coaching
Resume shared with 300 + employers

Intern Gurukul invites candidates aiming for promising careers in core technological domains and willing to work for product based companies, Research, innovation and start-ups.

Course Syllabus


Download Syllabus

Build successful career in VLSI by up skilling with latest tools.


Hardware Modeling Overview, Introduction to Verilog, Modules and Ports
Different Modeling styles, Test benches, Data Types, Operators, Verilog Coding for Combinational and Sequential Circuits, Procedural Blocks
Finite State Machines Coding, Synthesis, Tasks and Functions, Project

System Verilog;

Introduction to System Verilog, Test benches, Data Types, Operators, Procedural Blocks
System Verilog Coding for Combinational and Sequential Circuits,
System Verilog Coding for Finite State Machines , Synthesis, project, verification using System Verilog

Xilinx ISE14.6/14.7.
Matalb / Simulink.

Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic Line Decoders
An Architecture for 32-bit Energy-Efficient Wallace Tree Carry Save Adder
FPGA Implementation of Combined S-Box and InvS-Box of AES
Design of Power and Area Efficient Approximate Multipliers
Design and Implementation of a 5-Bit Flash ADC for Education
Hardware Architecture for 2D Gaussian Filtering of HD Images on Resource Constrained Platforms

Project Details

ALU design using clock gating and folded tree architecture

In this project we are focusing on reduction in dynamic power dissipation of chip using latch free clock gating technique. According to moors law scaling of technology with high performance and less power dissipation becoming hurdle in designing of processor engine. Power dissipation can be reduced by two ways by reducing static power dissipation and by reducing dynamic power dissipation.

FPGA implementation of filtered image using 2D Gaussian filter

In this paper, an apparatus execution of picture sifted utilizing 2D Gaussian Filter will be open. The Gaussian channel design will be depicted utilizing a substitute methodology to finish convolution module. Along these lines, increment is in the focal point of convolution module, thusly, three unmistakable approaches to manage acknowledge duplication assignments will be shown.

Adaptive Fir Filter with Optimized Area and Power using Modified Inner-Product Block

Appropriated Arithmetic structure is used to grow the benefit usage while pipeline structure is in like manner used to manufacture the system speed. The memory size can be decreased by crumbling the LUT. FIR channel is laid out using multiplexer which is used to pick the channel coefficients.

An Efficient Implementation of Floating Point Multiplier

An efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA.The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. The multiplier was verified against Xilinx floating point multiplier core.

Cost:  4,989/-Enroll Now

20+ AMAZING Industry Experts and Mentors


Top Companies Hiring This Talent


Knowx Inovation offers best internship for ece & cse aspirants who are pursuing B.E & is open up for students from II sem to VIII sem. Build a solid foundation by covering the most popular & widely used VLSI technologies. Complete hands-on with in-demand Tensorflow, Keras, artificial intelligence, and neural network techniques. 2 hands-on projects by using AI tools & technologies.